1. Field of the Invention
The present invention relates to an imaging device, such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a control method therefor, and a camera.
2. Description of the Related Art
CMOS image sensors with various architectures to image a subject at a high speed have been proposed. For example, there is a CMOS image sensor which has an A/D converter provided for a column circuit to achieve faster imaging and lower noise (see JP-A-2005-278135 (Patent Document 1), for example).
When the pitch between pixel circuits becomes narrower with an improved scale of the integration of the pixel circuits, it is difficult to install a plurality of CDS circuits in one column (one stage). There is a CMOS image sensor which achieves integration of pixel circuits by arranging a plurality of CDS circuits separated in upper and lower stages of a pixel section and allowing two systems of CDS circuits to process output signals of the pixel circuits (see JP-A-2005-318544 (Patent Document 2), for example). The outline of a CMOS image sensor on the basis of the method disclosed in Patent Document 2 will be described in connection with FIG. 14.
FIG. 14 is a schematic configurational diagram showing an example of the configuration of a general CMOS image sensor.
A CMOS image sensor 3 has a selection control circuit (SCTLC) 34, a current source 36, a CDS circuit (CDS) 38, and a column drive circuit (HSCNC) 310 arranged at the upper stage of a pixel section 31. A selection control circuit 35, a current source 37, a CDS circuit 39, and a column drive circuit 311 are arranged at the lower stage of the pixel section 31.
The upper stage indicates the side where a first column pixel circuit 32, and the lower stage indicates the side where a last column pixel circuit 32.
A plurality of pixel circuits 32 in the pixel section 31 are laid out in a Bayer pattern. The pixel circuits 32 that sense Gr (green) and the pixel circuits 32 that sense R (red) are alternately laid out in an mth row, while the pixel circuits 32 that sense B (blue) and the pixel circuits 32 that sense Gb (green) are alternately laid out in an (m+1)th row.
A row drive circuit (VSCNC) 33 drives those pixel circuits 32 are driven to read charges therefrom. In case of reading charges, it is desirable that one of the CDS circuits should process voltage signals output from the Gr and Gb pixel circuits 32 of similar colors in order to prevent horizontal noise or the like (see U.S. Pat. No. 6,838,651 (Patent Document 3)).
In this respect, when the row drive circuit 33 applies a drive signal to a drive signal line DRNL(m) to drive the pixel circuits 32 in the mth row, the upper-stage selection control circuit 34 controls a switch SW31 to connect the upper-stage CDS circuit 38 to a vertical signal line VSL(n).
At the same time, the lower-stage selection control circuit 35 controls a switch SW32 to connect the lower-stage CDS circuit 39 to a vertical signal line VSL(n+1).
Reading of charges from Gr and Gb pixel circuits 32 of similar colors will be described below in connection with FIGS. 15A and 15B.
FIGS. 15A and 15B are schematic configurational diagrams each showing one state of the general CMOS image sensor. FIGS. 15A and 15B show only the components necessary for the explanation.
An amplification transistor which constitutes a part of the Gr pixel circuit 32 in the mth row, and the current source 37 located at the succeeding stage form a source follower circuit. With the source follower circuit formed, the CMOS image sensor 3 reads charges from the Gr pixel circuit 32.
At this time, as shown in FIG. 15A, a constant current flows toward the current source 37 from the Gr pixel circuit 32, and a voltage signal (readout charges) output to a node ND31 from the Gr pixel circuit 32 is input to the upper-stage CDS circuit 38 via the switch SW31.
Next, in case of reading charges from pixel circuits 32 in the (m+1)th row, the row drive circuit 33 applies the drive signal to a drive signal line DRNL(m+1), and the upper-stage selection control circuit 34 controls the switch SW31 to connect the upper-stage CDS circuit 38 to the vertical signal line VSL(n+1).
At the same time, the lower-stage selection control circuit 35 controls the switch SW32 to connect the lower-stage CDS circuit 39 to the vertical signal line VSL(n+1).
An amplification transistor which constitutes a part of the Gb pixel circuit 32 in the (m+1)th row, and the current source 36 located at the preceding stage form a source follower circuit.
At this time, as shown in FIG. 15B, a constant current flows toward the current source 36 from the Gb pixel circuit 32, and a voltage signal output to a node ND32 from the Gb pixel circuit 32 is input to the upper-stage CDS circuit 38 via the switch SW31.
The CMOS image sensor 3 shown in FIG. 14 selects a transmission path for a voltage signal by switching the switch SW31, SW32 to allow the CDS circuit 38 of the same stage to process the voltage signals output from the Gb and Gr pixel circuits 32 of similar colors.
However, the CMOS image sensor 3 has the following disadvantages. Because a current source is not present on the transmission path for the voltage signal output from the Gr pixel circuit 32 (transmission path from the node ND31 to the CDS circuit 38), as shown in FIG. 15A, a (bias) current does not flow in the transmission path, so that the potential on the transmission path is kept the same.
However, because a current source is present on the transmission path for the voltage signal output from the Gb pixel circuit 32 (transmission path from the node ND32 to the CDS circuit 38), as shown in FIG. 15B, a (bias) current flows in the transmission path, causing a voltage drop according to the wiring load of the vertical signal line VSL(n+1), so that the potential on the transmission path is not kept the same.
The Gb pixel circuit 32 positioned farthest from the current source 36 has a greater voltage drop than the Gb pixel circuit 32 positioned closest to the current source 36, producing a difference in input operational point by the voltage drop between the original input operational point of the CDS circuit 38 and the actual input operational point thereof. The input operational point is the voltage on which the CDS circuit 38 operates. The difference between the input operational points of the CDS circuit 38 causes vertical noise and shading.
To avoid such a problem, a CMOS image sensor 3a shown in FIG. 16 employs the following configuration.
FIG. 16 is a schematic configurational diagram showing another example of the general CMOS image sensor.
As shown in FIG. 16, the CMOS image sensor 3a has Gb and B pixel circuits 32 in the (m+1)th row arranged, shifted by one column from Gr and R pixel circuits 32 in the mth row. Accordingly, the Gr and Gb pixel circuits 32 are connected to a common vertical signal line VSL(n), and the R and B pixel circuits 32 are connected to a common vertical signal line VSL(n+1). This layout of the pixel circuits 32 keeps the transmission path for a voltage signal at the same potential in order to reduce vertical noise and shading.